1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, in particular, to a semi-conductor integrated circuit for power consumption.
2. Background of the Related Art
FIGS. 1A and 1B illustrate related art dynamic logic using a precharge operation. As illustrated in FIG. 1A, the related art dynamic logic includes a PMOS transistor Mp1 for pulling up an output node 50 to a VDD level in a precharge operation, a NMOS transistor Mn1 for blocking a pull-down path in the precharge operation and a n-logic 10 connected between the output node 50 and the NMOS transistor Mn1.
As illustrated in FIG. 1B, the related art dynamic logic may also include a NMOS transistor Mn2 for pulling down an output node 60 to a VSS level in a precharge operation, a PMOS transistor MP2 for blocking a pull-up path in the precharge operation and a p-logic 11 connected between the PMOS transistor Mp2 and the output node 60. Gates of the PMOS transistors Mp1 and Mp2 and NMOS transistors Mn1 and Mn2 receive a clock signal CLK, and the back gates (i.e., substrate node) of the PMOS transistors Mp1 and Mp2 and NMOS transistors Mn1 and Mn2 receive a power voltage VDD and a ground voltage VSS, respectively. In addition, a plurality of signals [in(0)xcx9cin(N)] are inputted to the n-logic 10 and the p-logic 11.
The operation of the related art dynamic logic in FIGS. 1 and 2 will now bw described. In the related art dynamic logic, a precharge state is a standby state, and an evaulation state is an active state.
In the stanby state, a clock signal CLK of low level (logic xe2x80x9c0xe2x80x9d)is applied to the dynamic logic 100 illustrated in FIG. 1A. Upon receipt of the low level clock signal CLK, the PMOS transistor Mp1 connecting the power voltage VDD and the output node 50 are turned on, and the NMOS transistor Mn1 connecting the n-logic 10 and the ground voltage VSS is turned off. Thus, the output node 50 is pulled up to the VDD level through the turned-on PMOS transistor Mp1, and thereby the output OUT of the dynamic logic 100 turns into a high level (logic xe2x80x9c1xe2x80x9d). The pull-down path is blocked by the turned off NMOS transistor Mn1. In the active state, a clock signal CLK of high level (logic xe2x80x9c1xe2x80x9d) is applied to the dynamic logic 100. The PMOS transistor Mp1 is turned off and the NMOS transistor Mn1 is turned on, and the output OUT of the dynamic logic 100 is determined by levels of signals [in(0)xcx9cin (N)] inputted to the n-logic 10. If the signals [in(0)xcx9cin(N)] are all at a high level, the output node 50 is pulled down to the VSS level, and the output OUT of the dynamic logic 100 is driven to a low level. If at least one of the signals [in(0)xcx9cin(N)] is at a low level, the output OUT of the dynamic logic 100 remains at the same logic value (i.e., logic xe2x80x9c1xe2x80x9d) as in the standby state.
The related art dynamic logic 101 illustrated in FIG. 1B operates symmetrically with the dynamic logic 100 illustrated in FIG. 1A. Accordingly, a detailed description is omitted here.
In semiconductor integrated circuits, a lower power voltage is increasingly used to improve the reliability of the device and reduce power consumption. Therefore, when implementing a low voltage circuit, the threshold voltage (Vt) of the MOS transistor has to be reduced to prevent a decrease in operating speed. However, if a MOS transistor with a low threshold voltage (low-Vt) is used for implementing a low voltage dynamic logic, subthreshold voltage leakage current flows through the pull-down path or pull-up path in the standby state or in the active state.
For example, when the NMOS transistor Mn1 and the PMOS transistor Mp1 are implemented as a low threshold voltage MOS transistor in FIG. 1A, the NMOS transistor Mn1 that should be turned-off in the standby state is turned on, or the PMOS transistor Mp1 that should be turned-off in the active state is turned on. As a result, a leakage current flows through the channel of the turned-on NMOS transistor Mn1 or PMOS transistor Mp1 and causes serious power dissipation. This power dissipation phenomenon is increased in the case that the entire circuit remains in a precharge state for a long time, that is, in the standby state.
Accordingly, many attempts are currently being made to reduce s subthreshold leakage current for logic circuits. U.S. Pat. No. 5,610,533 illustrates a logic circuit (e.g., FIG. 6) for reducing subthreshold leakage current.
The conventional logic circuit in U.S. Pat. No. 5,610,533 reduces the subthreshold leakage current by varying the voltage applied to the back gates of the PMOS transistor and NMOS transistor according to a clock signal. In other words, the conventional logic circuit reduces subthreshold voltage by applying voltages VPP and VBB to the back gates of the PMOS transistor and NMOS transistor, respectively, and thus increases the threshold voltage value. At this time, the voltage VPP is larger than the power voltage VDD, and the voltage VBB is smaller than the ground voltage VSS.
As described above, the conventional logic circuit has various disadvantages. The conventional logic circuit has an increased size because an additional clock signal generator has to be provided in order to reduce subthreshold current. In particular, a circuit that discriminates between the standby state and the active state has to be provided so that the clock signal generator generates clock signals different from each other according to a standby or an active operation mode.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to provide a semiconductor integrated circuit that substantially obviates one or more of problems caused by disadvantages or limitations of the related art.
Another object of the present invention is to provide a logic circuit that reduces power consumption in a low voltage integrated circuit.
Another object of the present invention is to provide a circuit that inhibits power consumption in a low voltage dynamic logic that is caused by a subthreshold leakage current.
Another object of the present invention is to provide a circuit that inhibits power consumption in a low voltage dynamic logic that reduces its chip area and power consumption due to subthreshold leakage current.
Another object of the present invention is to provide a circuit that inhibits power consumption in a low voltage dynamic logic that reduces a circuit size to increase chip integration.
Another object of the present invention is to provide a circuit for inhibiting power consumption in a low voltage dynamic logic that controls the substrate voltage of a MOS transistor according to an output level of the dynamic logic in an active and standby modes.
In order to achieve at least the above objects in a whole or in part, there is provided a circuit for inhibiting power consumption in a low voltage dynamic logic in accordance with the present invention that includes a dynamic logic provided with first and second MOS transistors of different conductive types and a power selector that outputs first and second voltages different from each other as a substrate voltage of the first and second transistors according to an output level of the dynamic logic. If the output of the dynamic logic is at a high level, the power selection unit outputs a power voltage and a substrate voltage as the first and second voltages, and when the output of the dynamic logic is at a low level, the power selection unit outputs a boosting voltage and a ground voltage as the first and second voltages, respectively.
To further achieve the above objects in whole or in part, and in accordance with the present invention, a circuit for reducing power consumption that includes a dynamic logic that includes first and second transistors and a power selection unit that outputs first and second voltages different from each other as a substrate voltage of the first and second transistors according to an output of the dynamic logic.
To further achieve the above objects in whole or in part, and in accordance with the present invention, a circuit for reducing power consumption in a low voltage dynamic logic is provided that includes a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type, a first power selection unit that applies one of a first prescribed voltage and a second prescribed voltage to a back gate of the first MOS transistor according to an output signal of the dynamic logic, and a second power selection unit that applies one of a third voltage and a fourth voltage to a back gate of the second MOS transistor according to the output of the dynamic logic.
To further achieve the above objects in whole or in part, and in accordance with the present invention, a circuit that reduces power consumption in a low voltage integrated circuit is provided that includes a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type, a logic gate that logically processes an output signal of the dynamic logic, a first PMOS transistor that outputs a boosting voltage to a back gate of the first MOS transistor according to the output signal of the dynamic logic, a second PMOS transistor that outputs a first prescribed voltage to the back gate of the first MOS transistor according to an output signal of the logic gate, a first NMOS transistor that outputs a substrate voltage to a back gate of the second MOS transistor according to the output signal of the dynamic logic, and a second NMOS transistor that outputs a second prescribed voltage to the back gate of the second MOS transistor according to the output signal of the logic gate.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.